As the geometry of transistors with respect to technology in integrated circuits (microelectronic chips or micro chips) shrinks, the number and type of defects on a chip may increase exponentially with an increase in logic density. A defect is an error introduced into a device during the manufacturing process. A fault model is a mathematical description of how a defect alters design behavior. During the design of the integrated circuit, testing is performed to ensure that the integrated circuit works as anticipated. Testing of integrated circuits may be facilitated by design techniques known in the art as Design For Test (DFT), also known as Design for Testability. Automatic Test Pattern Generation and Automatic Test Pattern Generator (ATPG) is an electronic design automation technology used to find an input (or test) sequence that, when applied to a digital circuit, enables automatic test equipment to distinguish between the correct circuit behavior and the faulty circuit behavior caused by defects. Design for testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each gate and path in a design.
Therefore, a particular test logic design, used in conjunction with a DFT technique, may include more modeled defects and thus more scan flip-flops to accommodate for the increased number of modeled defects. The ratio between the modeled defects and the scan flip-flops may be referred to as fault density. The scan flip-flops may be organized in scan chains to facilitate defect testing. Typically, test time may be reduced by decreasing the scan chain length; however, a decrease in the scan chain length may alternatively increase the number of scan chains.
A larger number of test patterns may be required in order to effectively test the manufacturing defects of the microchip. The increase in the number of modeled faults and test patterns may increase the test time and power consumption associated with the test.
A microchip logic design may be divided into multiple logical boundaries referred to as partitions. The partition may include one or more sub-designs. Each sub-design may include one or more scan chains. The microchip may be partitioned into any number of partitions or test mode partitions and for any number of reasons, such as clock domains, design hierarchy including any custom test mode requirements, etc. Test mode may be defined as a mode in which the microchip is configured for manufacturing testing. Furthermore, fault density may be calculated on the partition and the sub design.
Scan compression may refer to the compression of the test patterns in order to effectively input or feed them to the scan chains. A scan compression ratio may be defined as the number of scan chains to the number of scan-in pins. A typical microchip design will have a larger number of logic scan chains relative to the number of scan-in pins. Current methods may use a uniform compression ratio by assigning the same scan compression ratio to partitions having different fault densities. However, the higher the compression ratio may be indicative of a higher amount of compression. Particularly, the higher compression ratio signifies feeding more scan chains from each scan-in pin. Conversely, the lower the compression ratio may be indicative of a lower amount of compression and as such, the lower compression ratio signifies feeding less scan chains from each scan-in pin.
Typical scan compression techniques may uniformly assign an even number of scan chains to receive test patterns from a single scan-in pin, and as such each scan-in pin would supply test patterns to the same number of scan chains. There are many different scan compression techniques which are useful for reducing the number of test patterns required and reducing the test time. However, none of them have the intelligence to select the compression ratio based on the type of design. A partition with a lesser number of faults and a greater number of scan flip-flops can undergo a higher scan compression compared to a partition with a higher number of faults and a lesser number of scan flip-flops. As such, uniform scan compression ratio allocation may cause inefficient pattern generation by an APTG tool because the fault density is not taken into account and the compression ratio is distributed evenly regardless of the type of design. Therefore, it may be desirable, among other things, to determine and assign non-uniform scan compression ratios during integrated circuit testing.